Semiconductor integrated circuit chips and interposers fabricated on both silicon and glass are susceptible to cracking due to defects incurred during dicing operations, at the edge of the singulated chip. These defects act as crack initiation points as the interposer or chip experiences stresses during cycling induced by front and backside layers as well as Cu filled vias and coefficients of thermal expansion (CTE) mismatches. In glass interposers these stresses can be particularly detrimental.
To prevent crack propagation within delicate dielectric levels, laser ablation is commonly performed to remove continuous dielectric levels of the multiple redistribution layers (RDL) in the kerf prior to mechanical dicing operations. Although ablating the dielectric layers prevents them from incurring damage while dicing occurs, it does not address the damage induced to the substrate.